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Espressif Systems /ESP32-P4 /LP_AON_CLKRST /LP_AONCLKRST_HP_USB_CLKRST_CTRL1

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Interpret as LP_AONCLKRST_HP_USB_CLKRST_CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LP_AONCLKRST_RST_EN_USB_OTG20_ADP)LP_AONCLKRST_RST_EN_USB_OTG20_ADP 0 (LP_AONCLKRST_RST_EN_USB_OTG20_PHY)LP_AONCLKRST_RST_EN_USB_OTG20_PHY 0 (LP_AONCLKRST_RST_EN_USB_OTG20)LP_AONCLKRST_RST_EN_USB_OTG20 0 (LP_AONCLKRST_RST_EN_USB_OTG11)LP_AONCLKRST_RST_EN_USB_OTG11 0 (LP_AONCLKRST_RST_EN_USB_DEVICE)LP_AONCLKRST_RST_EN_USB_DEVICE 0LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL 0 (LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN)LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN 0 (LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN)LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN

Description

HP USB Clock Reset Control Register.

Fields

LP_AONCLKRST_RST_EN_USB_OTG20_ADP

usb otg20 adp reset en
LP_AONCLKRST_RST_EN_USB_OTG20_PHY

usb otg20 phy reset en
LP_AONCLKRST_RST_EN_USB_OTG20

usb otg20 reset en
LP_AONCLKRST_RST_EN_USB_OTG11

usb org11 reset en
LP_AONCLKRST_RST_EN_USB_DEVICE

usb device reset en
LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL

usb otg20 hs phy src sel. 2’d0: 12m, 2’d1: 25m, 2’d2: pad_hsphy_refclk.
LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN

usb otg20 hs phy refclk enable.
LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN

usb otg20 ulpi clock enable.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data